View BS616UV1010CI_9005978.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

revision 2.2 april 2001 1 r0201-bs616uv1010 power dissipation speed (ns) standby (i ccsb1 , max) operating (i cc , max) product family operating temperature vcc range vcc=3.0v vcc=3.0v vcc=2.0v vcc=3.0v vcc=2.0v pkg type bs616uv1010ec tsop2-44 bs616uv1010ac +0 o c to +70 o c 1.8v ~ 3.6v 150 0.5ua 0.3ua 15ma 10ma bga-48-0608 bs616uv1010ei tsop2-44 bs616uv1010ai -40 o c to +85 o c 1.8v ~ 3.6v 150 1ua 20ma 1.5ua 15ma bga-48-0608 ultra low power/voltage cmos sram 64k x 16 bit ? ultra low operation voltage : 1.8 ~ 3.6v ? ultra low power consumption : vcc = 2.0v c-grade : 10ma (max.) operating current i- grade : 15ma (max.) operating current 0.01ua (typ.) cmos standby current vcc = 3.0v c-grade : 15ma (max.) operating current i- grade : 20ma (max.) operating current 0.02ua (typ.) cmos standby current ? high speed access time : -15 150ns (max.) at vcc = 3.0v ? input levels are cmos-compatible ? automatic power down when chip is deselected ? three state outputs and ttl compatible ? fully static operation ? data retention supply voltage as low as 1.5v ? easy expansion with ce and oe options ? i/o configuration x8/x16 selectable by lb and ub pin the bs616uv1010 is a high performance, ultra low power cmos static random access memory organized as 65,536 words by 16 bits and operates from a wide range of 1.8v to 3.6v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 0.01ua and maximum access time of 150ns in 2v operation. easy memory expansion is provided by an active low chip enable(ce) and active low output enable(oe) and three-state output drivers. the bs616uv1010 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the bs616uv1010 is available in the jedec standard 44-pin tsop type ii and 48-pin mini-bga. ? description ? features row decoder memory array 512 x 2048 column i/o write driver sense amp column decoder data buffer output a3 a2 a1 data input buffer control gnd vcc oe dq0 a7 a15 a13 16 16 16 16 we ce dq15 a5 a6 14 128 2048 ? block diagram 512 18 a14 a12 a9 a4 a0 a11 a8 address input buffer a10 address input buffer . . . . ub . . . . lb ? product family ? pin configurations brilliance semiconductor inc . reserves the right to modify document contents without notice. bs616uv1010 g h f e d c b a 12345 a9 a8 nc io15 io14 nc io13 a12 a14 nc a11 a10 a13 a15 we io5 io7 io6 vcc vss io9 io12 io11 io10 nc nc a5 nc a7 a6 io4 io3 io1 vss vcc io2 io8 lb ub oe a3 a0 a4 a1 ce a2 io0 nc 6 a4 a3 a2 a1 a0 ce dq0 dq1 dq2 dq3 vcc gnd dq4 dq5 dq7 dq6 we a15 a14 a13 a12 nc a5 a6 a7 oe ub lb dq15 dq14 dq13 dq12 gnd vcc dq11 dq10 dq9 dq8 nc a8 a9 a10 a11 nc 1 2 3 4 5 18 20 22 43 41 39 28 26 24 23 6 7 8 9 10 11 12 13 14 16 37 36 35 34 33 32 31 30 bs616uv1010ec bs616uv1010ei 15 17 19 21 44 42 40 38 29 27 25 bsi
revision 2.2 april 2001 2 r0201-bs616uv1010 name function a0-a15 address input these 16 address input select one of the 65,536 x 16-bit words in the ram. ce chip enable input ce is active low. chip enables must be active to read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. lb and ub data byte control input lower byte and upper byte data input/output control pins. dq0 - dq15 data input/output these 16 bi-directional ports are used to read data from or write data into the ram. ports vcc power supply gnd ground ? truth table ? pin descriptions bsi bs616uv1010 mode ce we oe lb ub dq0~dq7 dq8~dq15 vcc current not selected (power down) h x x x x high z high z i ccsb , i ccsb1 output disabled l h h x x high z high z i cc l l dout dout i cc h l high z dout i cc read l h l l h dout high z i cc l l din din i cc h l x din i cc write l l x l h din x i cc
revision 2.2 april 2001 3 r0201-bs616uv1010 symbol parameter test conditions min. typ. (1) max. units v dr vcc for data retention ce
vcc - 0.2v v in
vcc - 0.2v or v in 0.2v 1.5 -- -- v i ccdr data retention current ce
vcc -0.2v v in
vcc - 0.2v or v in 0.2v -- 0.01 0.2 ua t cdr chip deselect to data retention time 0---- ns t r operation recovery time see retention waveform t rc (2) -- -- ns symbol parameter conditions max. unit c in input capacitance v in =0v 6 pf c dq input/output capacitance v i/o =0v 8 pf range ambient temperature vcc commercial 0 o c to +70 o c1.8v ~ 3.6v industrial -40 o c to +85 o c1.8v ~ 3.6v 1. typical characteristics are at ta = 25 o c. 2. these are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. fmax = 1/t rc . ? data retention characteristics ( ta = 0 o c to + 70 o c ) 1. vcc = 1.5v, t a = + 25 o c 2. t rc = read cycle time ? absolute maximum ratings (1) ? operating range ? capacitance (1) (ta = 25 o c, f = 1.0 mhz) 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not tested. ? dc electrical characteristics ( ta = 0 o c to + 70 o c ) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t bias temperature under bias c -40 to +125 o t stg storage temperature c -60 to +150 o p t power dissipation 1.0 w i out dc output current 20 ma bsi bs616uv1010 parameter name parameter test conditions min. typ. (1) max. units vcc=2.0v 0.6 v il guaranteed input low voltage (2) vcc=3.0v -0.5 -- 0.8 v vcc=2.0v 1.4 v ih guaranteed input high voltage (2) vcc=3.0v 2.0 -- vcc+0.2 v i il input leakage current vcc = max, v in = 0v to vcc -- -- 1 ua i ol output leakage current vcc = max, ce = v ih , or oe = v ih , v i/o = 0v to vcc -- -- 1 ua vcc=2.0v v ol output low voltage vcc = max, i ol = 1ma vcc=3.0v -- -- 0.4 v vcc=2.0v 1.6 v oh output high voltage vcc = min, i oh = -0.5ma vcc=3.0v 2.4 -- -- v vcc=2.0v -- -- 10 i cc operating power supply current ce = v il , i dq = 0ma, f = fmax (3) vcc=3.0v -- -- 15 ma vcc=2.0v -- -- 0.5 i ccsb standby current-ttl ce = v ih , i dq = 0ma vcc=3.0v -- -- 1 ma vcc=2.0v -- 0.01 0.3 i ccsb1 standby current-cmos ce
vcc-0.2v, v in
vcc - 0.2v or v in 0.2v vcc=3.0v -- 0.02 0.5 ua
revision 2.2 april 2001 4 jedec parameter name parameter name description bs616uv1010-15 min. typ. max. unit t avax t rc read cycle time 150 -- -- ns t avqv t aa address access time -- -- 150 ns t elqv t acs chip select access time (ce) -- -- 150 ns t ba t ba data byte control access time (lb,ub) -- -- 150 ns t glqv t oe output enable to output valid -- -- 80 ns t elqx t clz chip select to output low z (ce) 15 -- -- ns t be t be data byte control to output low z (lb,ub) 15 -- -- ns t glqx t olz output enable to output in low z 15 -- -- ns t ehqz t chz chip deselect to output in high z (ce) 0 -- 45 ns t bdo t bdo data byte control to output high z (lb,ub) 0 -- 40 ns t ghqz t ohz output disable to output in high z 0--40ns t axox t oh output disable to output address change 15 -- -- ns r0201-bs616uv1010 input pulse levels input rise and fall times input and output timing reference level vcc/0v 5ns 0.5vcc ? ac electrical characteristics ( ta = 0 o c to + 70 o c, vcc = 2.0v ) read cycle ? ac test conditions ? ac test loads and waveforms ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t car any chang permitted e: change : e state does not apply must be steady will be change from h to l unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , ? low v cc data retention waveform ( ce controlled ) ce data retention mode vcc t cdr vcc t r v ih v ih vcc v dr 1.5v ce vcc - 0.2v bsi bs616uv1010 ? 800 thevenin equivalent all input pulses 10% 90% vcc gnd 5ns 90% 10% 1.2v output figure 2 2v output including jig and scope ? 1333 ? 2000 5pf figure 1b 2v output including jig and scope ? 1333 ? 100pf figure 1a 2000
revision 2.2 april 2001 5 r0201-bs616uv1010 ? switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh t oh read cycle3 (1,4) t rc t oe d out lb,ub ce oe address t clz (5) t acs t chz (1,5) t ohz (5) t olz t aa read cycle2 (1,3,4) t clz t chz (5) d out lb,ub ce (5) t ba t acs notes: 1. we is high for read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf as shown in figure 1b. the parameter is guaranteed but not 100% tested. t be t bdo t bdo t ba t be bsi bs616uv1010
revision 2.2 april 2001 6 r0201-bs616uv1010 t wr ? ac electrical characteristics ( ta = 0 o c to + 70 o c, vcc = 2.0v ) write cycle ? switching waveforms (write cycle) write cycle1 (1) t wc (3) t cw (11) t bw (2) t wp t aw t ohz (4,10) t as (3) t dh t dw d in d out we lb,ub ce oe address (5) bsi bs616uv1010 jedec parameter name parameter name description bs616uv1010-15 min. typ. max. unit t avax write cycle time t wc 150 -- -- ns t e1lwh t cw chip select to end of write 150 -- -- ns t avwl t as address setup time 0---n -s t avwh t aw address valid to end of write 150 -- -- ns t wlwh t wp write pulse width 80 -- -- ns t whax t wr write recovery time (ce,we) 0 -- -- ns t bw t bw date byte control to end of write (lb,ub) 70 -- -- ns t wlqz t whz write to output in high z 0--40ns t dvwh t dw data to write time overlap 40 -- -- ns t whdx t dh data hold from write time 0---n -s t ghqz t ohz output disable to output in high z 0--40ns t whox t ow end of write to output active 5---n -s
revision 2.2 april 2001 7 r0201-bs616uv1010 write cycle2 (1,6) t wc t cw (11) (2) t wp t aw t whz (4,10) t as t wr (3) t dh t dw d in d out we ce address (5) t dh (7) (8) (8,9) t bw lb,ub bsi bs616uv1010 notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf as shown in figure 1b. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write. 12. the change of read/write cycle must accompany with ce or address toggled.
revision 2.2 april 2001 8 r0201-bs616uv1010 package e: tsop ii - 44 pin a: bga-48 pin(6x8mm) ? ordering information bsi bs616uv1010 x x -- y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 15: 150ns ? package dimensions bs616uv1010 tsop2-44
revision 2.2 april 2001 9 r0201-bs616uv1010 bsi bs616uv1010 ? package dimensions (continued) 48 mini-bga (6 x 8) d1 view a 1.4 max. e e1 1: controlling dimensions are in millimeters. 2: pin#1 dot marking by laser or pad print. 3: symbol "n" is the number of solder balls. ball pitch e = 0.75 d 8.0 6.0 en 48 3.75 e1 d1 5.25 notes:
revision 2.2 april 2001 10 bsi r0201-bs616uv1010 revision history revision description date note 2.2 2001 data sheet release apr. 15, 2001 bs616uv1010

▲Up To Search▲

Price & Availability of BS616UV1010CI

	To Download BS616UV1010CI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .